1. Field of the Invention
The present invention relates generally to a recessed gate transistor. More particularly, the present invention relates to a recessed gate transistor having cylindrical fins.
2. Description of the Prior Art
In general, as semiconductor devices are highly integrated, the gate channel lengths of the highly integrated semiconductor devices are significantly shortened.
For example, in a planar MOS transistor, as the channel length is reduced, electric fields may affect operation of the planar MOS transistor due to drain induced barrier lowering (DIBL). Also, a channel-driving capacity of a gate conductor may be deteriorated such that a short channel effects may occur.
In order to prevent the short channel effect and DIBL, various semiconductor fabrication technologies capable of lengthening an effective line width of a channel have been developed. For example, a recess gate forming technology is suggested by prior art. According to the recess gate forming technology, a recess is formed in a semiconductor substrate and a gate is formed in the recess, thereby lengthening the effective length of a channel.
However, the gate insulating layer of the semiconductor device fabricated through the conventional forming technology has a thin gate insulating layer at the gate edge, thereby causing the inferior gate induced drain leakage (GIDL) characteristics. This problem may deteriorate the operating performance of the devices.